1/4 rev. a structure silicon monolithic integrated circuit type single channel series regulator driver ic product series bd3520fvm features ? on rush current on start up (nrcs) ? n channel mosfet driver ? output voltage : 1.2v 1% absolute maximum ratings ta = 2 5 parameter symbol limit unit supply voltage vcc 7 *1 v drain voltage (vin) vd 7 v enable input voltage ven 7 v power dissipation pd 437.5 *2 mw operating temperature range topr -10 +100 storage temperature range tstg -55 +150 maximum junction temperature tjmax +150 *1 operating temperature range should not exceed t jmax =150 *2 pd derating at 3.5mw/ for temperature above ta=25 recommended operating conditions ta = 2 5 parameter symbol min max unit supply voltage vcc 4.5 5.5 v drain voltage vin vd 1.2 5.5 v enable input voltage ven -0.3 5.5 v capacitor on nrcs terminal cnrcs 0.001 1 uf this product is not designed for protection against radioactive rays.
2/4 rev. a electrical characteristics unless otherwise specified,ta=25 vcc=5v vin=3.3v ven=3v parameter symbol limit unit conditions min typ max bias current icc - 0.85 1.7 ma shut down mode current ist - 0 10 ua ven=0v output voltage 1 vo1 1.188 1.200 1.212 v io=50ma output voltage 2 vo2 1.176 1.200 1.224 v vcc=4.5v to 5.5v , ta = - 1 0 to 100 ( ) line regulation reg.l - 0.1 0.5 %/v vcc=4.5v to 5.5v load regulation reg.l - 0.5 10 mv io=0 to 3a [enable] high level enable input voltage enhi 2 - vcc v low level enable input voltage enlow -0.3 - 0.8 v enable pin input current ien - 7 10 ua ven=3v [source voltage] vs input bias current isbias - 1.2 2.4 ma vs standby current isstb 150 - - ma vs=1v ven=0v [output mosfet driver] mosfet driver source current igso 2 3 4 ma vfb=1.1v,vgate=2.5v mosfet driver sink current igsi 2 3 4 ma vfb=1.3v,vgate=2.5v [uvlo] vcc uvlo vccuvlo 4.20 4.35 4.50 v vcc:sweep up vcc uvlo hysterisis vcchys 100 160 220 mv vcc:sweep down vd uvlo vduvlo vo 0.6 vo 0.7 vo 0.8 v vd:sweep up [drain voltage sensing] vd input bias current ivd 10 16 22 ua [nrcs/scp] nrcs charge current inrcs 14 20 26 ua vnrcs=0.5v scp charge current iscpch 14 20 26 ua vnrcs=0.5v scp discharge current iscpdi 0.3 - - ma vnrcs=0.5v scp threshold voltage vscp 1.2 1.3 1.4 v short detect voltage voscp vo 0.3 vo 0.35 vo 0.4 v nrcs stand-by voltage vstb - - 50 mv ( ) design guarantee
3/4 rev. a physical dimensions block diagram pin number pin name pin no. pin name 1 nrcs 2 gnd 3 en 4 vcc 5 vfb 6 vs 7 g 8 vd (unit:mm) msop8 d 3 5 2 0 1pin mark lot no. reference block en vcc gnd thermal protection enable tsd tsd scp uvlo1 uvlo2 en nrcs vref nrcs nrcs vd uvlo latch 0.65v nrcs - + scp vcc scp 0.65v - + uvlo1 uvlo2 uvlo1 en 0.65v g vs v fb vo vin 1 2 3 4 5 6 7 c1 c2 c4 c3 8 vd
4/4 rev. a notes for use (1) absolute maximum range although the quality of this product is rigorously controlled, and ci rcuit operation is guaranteed within the operation ambient temperature range, the device may be destroyed when applied vo ltage or operating temperature exceeds its absolute maximum rating. because the failure mode (such as short mode or open mode) cannot be identified in this instance, it is important to ta ke physical safety measures such as fusing if a specific mode in excess of absolute ra ting limits is considered for implementation . (2) ground potential make sure the potential for the gnd pin is always kept lower than the potentials of all other pins, regardless of the operating mode, including trans ient conditions. (3) thermal design provide sufficient margin in the thermal design to account for the allowable power dissipation (p d) expected in actual use. (4) using in the strong electromagnetic field use in strong electromagnetic fi elds may cause malfunctions. (5) aso be sure that the output transistor for this ic does no t exceed the absolute maximum ratings or aso value. (6) thermal protection circuit a thermal shutdown circuit (t.s.d) is built into the ic to pr event damage due to overheating. therefore, all the outputs are tu rned off when the t.s.d circuit is activated. (this ic latches output to off mode when th e temperature recedes to the specified leve l. to release latch mode, en or uvlo is re-operated.) however, the t.s.d circuit is us ed only for extreme conditions, and the regulator circuit should still be designed fo r the ic not to exceed tj(max)=150 . (7) gnd pattern when both a small-signal gnd and high current gnd are pres ent, single-point grounding (at the set standard point) is recommended, in order to separate the small-signal and high current patterns, and to be sure the voltage change stemming from the wiring resistance and high current does not cause any vo ltage change in the small-signal gnd. in the same way, care must be taken to avoid wiring pattern fluctuati ons in any connected external component gnd. (8) output capacitor (c4) mount an output capacitor between vs and gnd for stability purpos es. the output capacitor is for the open loop gain phase compensation and reduces the output voltage load regulation. if the capacitor value is not large enough, the output voltage may oscillate. and if the equivalent series resistance (esr) is too large, the output voltage rise/drop increases during a sudden l oad change. a 220uf polymer capacitor is recommended. however, the stability depends on the characteristics of temperature, load, the gate capacitance of the external mosfet, and the mutual conductance (gm). and if a small esr capacitor such as a ceramic capacitor is utilized (several kind of capacitors are utilized in parallel), the output voltage may oscillate due to la ck of phase margin. in this case, measures can be taken by adding a capa citor and a resistor in series with this capacitor between th e gate of mosfet and gnd. please confirm operation across a variety of temperature, load conditions, and mosfet characteristics. (9) input capacitor (c1, c2) the input capacitor reduces the output impedence of the volt age supply source connected in the vcc and vin. if the output impedence of this power supply increases, the input voltage (vcc, vin) may become unstable. this may result in the output voltage oscillation or lowering ripple rejection. a low esr 10uf capacitor with minimal susceptib ility to temperature is prefer able, but stability depends on power supply characteristics, the subs trate wiring pattern, and the parasitic capacitor between gate and drain of mosfet. please confirm operation across a va riety of temperature, load, and mosfet conditions. (10) nrcs (non rush current on start-up) setting c3 the nrcs function is built in this ic to prevent rush current from going through the load (vin to vo) for start-up. the constan t current comes from the nrcs pin when en is high or uvlo fu nction is deactivated. temporary reference voltage is made proportional to time due to current charge the nrcs pin capa citor and make output voltage start up proportional to this reference volatge. timer latch short circuit protecti on function is built in this ic (nrcs is also working at the same time.) to protect the break down of the power mosfet caused by rush current when the output is shorted to gnd. this func tion becomes active when the output voltage level goes under by 30% of specified vout. the cons tant current comes from the nrcs pin in this case. when the reference voltage made by the current charge of the nrcs pin hits 1.3v (typ.), the gate voltage becomes low. to obtain a stable scp delay time, a capacitor (b) with susceptiblity to temperature is recommended. (11) input terminal (vcc,vd,en) the en, vd, and vcc are isolatetd. the uvlo protects incorre ct operation when the voltage level of vd and vcc are low. the output becomes high when these pins reach the individual threshold level independent of the start-up pin order. however, if vin shut down while the ic works under the normal operation, sc p function becomes active and latches the status. and the output does not come back active even though vin goes up high again. in th is case, start vcc or en up again to deactivate this latch function. (12) maximum output current (maximum load) the maximum output current of the power supply utilizing the ic depends on external mosfet. the mosfet should be chosen based on a required power supply characteristics for an actual application. (13) please add a protection diode when a large inductance component is connected to the output terminal, and reverse-polarity power is possibl e at startup or in output off condition. (example) output pin
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